1. Field of the invention
The present invention relates to a MOS technology power device, particularly to a MD (Multi Drain) power device.
2. Description of the Related Art
In the design or a power device utilized as a switch switching between on state and off state, the losses in the on state and in the off state must be considered.
The switching time of the device must be reduced in order to reduce the energy dissipated during the switching state. Particularly, the reduction of the intrinsic resistance of the gate of the device assumes a fundamental importance in a MOS technology power device; in fact this allows to reduce the delay of the power device in off state between the turn off imposed by the drive circuit and the effective turn off of the power device.
The reduction of the intrinsic resistance of a MOS power device is made, considering the plant view of the device, by introducing some frames called gate fingers which come into the active area zone of the device and allow the direct contact between the gate metal and the material (for example polysilicon) utilized for transmitting the gate signal of the elementary active units of the device (the MOS units of the power device). In this way the distance between the gate metal and each elementary unit to be switched is reduced so that a suitable reduction of the intrinsic resistance of the device is allowed.
A traditional technology for introducing gate fingers into the traditional MOS power device occurs with a frame wherein the zone, in active area, where the contact between the gate metal and the polysilicon is performed, is protected by a deep body well, a P+ well in the case of a n-channel MOS power device, which prevents the field lines from crowding in the thin oxide thereby avoiding a premature breakdown of the device. The contact between the gate metal and the polysilicon can occur both in proximity of the thin oxide and in proximity of the thick oxide.
However the structures of the above described type cannot be utilized in the case of MD (Multi Drain) MOS power device, wherein, in order to reduce the drain resistivity, columnar extensions of the body wells are introduced by an implant sequence among successive epitaxial growths so as to form the selective drain doping which equilibrates the epitaxially achieved drain charge. Such MD MOS power devices are known from the European patent applications No. 98830737.7 and No. 98830739.3 dated 09.12.1998 of the same Applicant.
In view of the state of the art described, it is an object of the present invention to disclose a MOS technology power device which solves the aforementioned problem.
According to the present invention, such an object is attained by a MOS technology power device comprising a plurality of elementary active units and a part of said power device which is placed between zones where said elementary active units are formed, characterized in that said part of the power device comprises at least two heavily doped body regions of a first conductivity type which are formed in a semiconductor layer of a second conductivity type, a first lightly doped semiconductor region of the first conductivity type which is placed laterally between said two body regions, said first semiconductor region being placed under a succession of a thick silicon oxide layer, a polysilicon layer and a metal layer, and a plurality of second lightly doped semiconductor regions of the first conductivity type being placed under said at least two heavily doped body regions and under said first lightly doped semiconductor region of the first conductivity type, each region of said plurality of second lightly doped semiconductor regions of the first conductivity type being separated from the other by portions of said semiconductor layer of the second conductivity type.
Thanks to the present invention it is possible to form a MOS technology power device, particularly a MD device, wherein the contact between the gate metal and the polysilicon is obtained by means of gate fingers without producing premature breakdown of the device.